CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1230

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 30 Security (S12X9SECV2)

Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the

security bits located in the options/security byte in the Flash memory array. These non-volatile bits will

keep the device secured through reset and power-down.

The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory

array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used

for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte

is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this

byte are copied into the Flash security register (FSEC) during a reset sequence.

Internal accesses visible

EEPROM Array Access

Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of

the ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for

detailed information.

Restricted NVM command set only. Please refer to the FTX/EETX block guides for detailed information.

BDM hardware commands restricted to peripheral registers only.

External Bus Interface

Internal status visible

Flash Array Access

DBG Module Trace

Modes of Operation

Securing the Microcontroller

XGATE Debugging

NVM Commands

on external bus

multiplexed on

external bus

Table 30-1. Features Availability in Unsecure and Secure Modes

Figure 30-1. Flash Options/Security Byte

MC9S12XDP512 Data Sheet, Rev. 2.21

Unsecure Mode

Freescale Semiconductor