CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 566

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See
14.4.8
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in
listed in
14.4.9
14.4.9.1
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
is kept high until V
The power-on reset is active in all operation modes of VREG_3V3.
14.4.9.2
For details on low-voltage reset, see
14.4.10 Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in
priorities are defined at MCU level.
566
Table 14-6
Table
Resets
Description of Reset Operation
Power-On Reset (POR)
Low-Voltage Reset (LVR)
14-9.
The first period after enabling the counter by APIFE might be reduced.
The API internal RC oscillator clock is not available if VREG_3V3 is in
Shutdown Mode.
for the trimming effect of APITR.
DD
PORD
Low-voltage interrupt (LVI)
exceeds V
Section 14.3, “Memory Map and Register
Interrupt Source
). Therefore, signal POR, which forces the other blocks of the device into reset,
Low-voltage reset
Power-on reset
Reset Source
PORD
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 14.4.5, “Low-Voltage Reset
Table 14-10. Interrupt Vectors
. The MCU will run the start-up sequence after POR deassertion.
Table 14-9. Reset Sources
Available only in Full Performance Mode
NOTE
LVIE = 1; available only in Full Performance
Local Enable
Always active
Table
Local Enable
Definition”. Possible reset sources are
14-10. Vector addresses and interrupt
Mode
(LVR)”.
DD
is below the POR
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