CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 359

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.1.2
Internal register whose output drives OCx when TIOS is set, can be force loaded with a desired data by
writing to CFORC register before OCx is configured for output compare action. This allows a glitch free
switch over of port from general purpose I/O to timer output once the output compare is enabled.
7.4.1.3
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC
buffered channels 3–0. A pulse accumulator counts the number of active edges at the input of its channel.
The minimum pulse width for the PAI input is greater than two bus clocks.The maximum input frequency
on the pulse accumulator channel is one half the bus frequency or Eclk.
The user can prevent the 8-bit pulse accumulators from counting further than 0x00FF by utilizing the
PACMX control bit in the ICSYS register. In this case, a value of 0x00FF means that 255 counts or more
have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see
Pulse accumulator B operates only as an event counter, it does not feature gated time accumulation
mode.The edge control for pulse accumulator B as a 16-bit pulse accumulator is defined by TCTL4[1:0].
To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or
output compare 7 and 0 respectively, the user must set the corresponding bits: IOSx = 1, OMx = 0, and
OLx = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
There are two modes of operation for the pulse accumulators:
7.4.1.4
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used
to latch the values of the IC registers and the pulse accumulators to their holding registers.
The action of latching can be programmed to be periodic or only once.
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Pulse accumulator latch mode
The value of the pulse accumulator is transferred to its holding register when the modulus
down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control
bit ICLAT is written.
At the same time the pulse accumulator is cleared.
Pulse accumulator queue mode
When queue mode is enabled, reads of an input capture holding register will transfer the contents
of the associated pulse accumulator to its holding register.
At the same time the pulse accumulator is cleared.
OC Channel Initialization
Pulse Accumulators
Modulus Down-Counter
MC9S12XDP512 Data Sheet, Rev. 2.21
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Figure
7-70).
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