CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 800

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.5.1
This mode allows interfacing to external memories or peripherals which are available in the commercial
market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each
external access.
21.5.1.1
The first example of bus timing of an external read and write access with the external wait feature disabled
is shown in
The associated supply voltage dependent timing are numbers given in
Systems designed this way rely on the internal programmable access stretching. These systems have
predictable external memory access times. The additional stretch time can be programmed up to 8 cycles
to provide longer access times.
21.5.1.2
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles
over the programmed number in EXSTR[2:0]. The feature must be enabled by writing EWAITE = 1.
If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If
EWAIT is asserted within the predefined time window during the access it will be strobed active and
another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is
finished. EWAIT can be held asserted as long as desired to stretch the access.
An access with 1 cycle stretch by EWAIT assertion is shown in
The associated timing numbers for both operations are given in
It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize
the EWAIT input signal.
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Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’
Table ‘Example 1a: Normal Expanded Mode Timing V
Table ‘Example 1a: Normal Expanded Mode Timing V
Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’
Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’
Table ‘Example 1b: Normal Expanded Mode Timing V
Table ‘Example 1b: Normal Expanded Mode Timing V
Normal Expanded Mode
Example 1a: External Wait Feature Disabled
Example 1b: External Wait Feature Enabled
MC9S12XDP512 Data Sheet, Rev. 2.21
DD5
DD5
DD5
DD5
= 5.0 V (EWAITE = 0)’
= 3.0 V (EWAITE = 0)’
= 5.0 V (EWAITE = 1)’
= 3.0 V (EWAITE = 1)’
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