CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 111

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.3.3.2
The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode.
If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all
configuration bits in the register space to its default settings and will perform a maximum of 50 clock
check_windows (see
the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the
normal reset vector. Full stop-mode is left and the MCU is in run mode again.
If the MCU is woken-up by an interrupt and the fast wake-up feature is disabled (FSTWKP = 0 or
SCME = 0), the CRG will also perform a maximum of 50 clock check_windows (see
“Clock Quality
core clocks and will continue with normal operation. If all clock checks within the Timeout-Window are
failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending
on the setting of the SCME bit.
If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and
SCME = 1), the system will immediately resume operation in self-clock mode (see
Quality
oscillator disabled until FSTWKP bit is cleared. The clearing of FSTWKP will start the oscillator and the
clock quality check. If the clock quality check is successful, the CRG will switch all system clocks to
oscillator clock. The SCMIF flag will be set. See application examples in
Because the PLL has been powered-down during stop-mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving stop-mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
Freescale Semiconductor
Checker”). The SCMIF flag will not be set. The system will remain in self-clock mode with
Wake-up from Full Stop (PSTP = 0)
In full stop mode or self-clock mode caused by the fast wake-up feature, the
clock monitor and the oscillator are disabled.
Checker”). If the clock quality check is successful, the CRG will release all system and
Section 2.4.1.4, “Clock Quality
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
Checker”). After completing the clock quality check
Chapter 2 Clocks and Reset Generator (S12CRGV6)
Figure 2-23
Section 2.4.1.4, “Clock
Section 2.4.1.4,
and
Figure
2-24.
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