CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 607

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4
The XINT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
16.4.1
The CPU handles both reset requests and interrupt requests. The XINT contains registers to configure the
priority level of each I bit maskable interrupt request which can be used to implement an interrupt priority
scheme. This also includes the possibility to nest interrupt requests. A priority decoder is used to evaluate
the priority of a pending interrupt request.
16.4.2
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2)
are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. The
exception to this rule is the spurious interrupt vector request at (vector base + 0x0010) which cannot be
disabled, is always handled by the CPU and has a fixed priority level of 7. A priority level of 0 effectively
disables the associated interrupt request.
If more than one interrupt request is configured to the same interrupt priority level the interrupt request
with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
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1. The local interrupt enabled bit in the peripheral module must be set.
2. The setup in the configuration register associated with the interrupt request channel must meet the
3. The I bit in the condition code register (CCR) of the CPU must be cleared.
4. There is no SWI, TRAP, or XIRQ request pending.
following conditions:
a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request.
b) The priority level must be set to non zero.
c) The priority level must be greater than the current interrupt processing level in the condition
Functional Description
code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]).
S12X Exception Requests
Interrupt Prioritization
All non I bit maskable interrupt requests always have higher priority than
I bit maskable interrupt requests. If an I bit maskable interrupt request is
interrupted by a non I bit maskable interrupt request, the currently active
interrupt processing level (IPL) remains unaffected. It is possible to nest
non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
Chapter 16 Interrupt (S12XINTV1)
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