CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 926

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.13 ECLK Control Register (ECLKCTL)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
928
Reset
NECLK
1. Reset values in emulation modes are identical to those of the target mode.
Field
7
NS
NX
SS
ES
ST
EX
W
R
1
Dependent
NECLK
Mode
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
0
1
0
0
1
0
7
= Unimplemented or Reserved
NCLKX2
1
1
1
1
1
1
1
6
Figure 23-15. ECLK Control Register (ECLKCTL)
Table 23-16. ECLKCTL Field Descriptions
0
0
0
0
0
0
0
0
5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
0
0
0
0
4
Description
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
EDIV1
0
0
0
0
0
0
0
1
Freescale Semiconductor
EDIV0
0
0
0
0
0
0
0
0
Single-Chip
Single-Chip
Single-Chip
Expanded
Expanded
Emulation
Emulation
Special
Special
Normal
Normal
Mode
Test