CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 324

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

Read or write: Anytime

All bits reset to zero.

OMx — Output Mode

OLx — Output Level

These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful

OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.

Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

To enable output action by OMx and OLx bits on timer port, the

corresponding bit in OC7M should be cleared.

Figure 7-11. Timer Control Register 1 (TCTL1)

Figure 7-12. Timer Control Register 2 (TCTL2)

Table 7-9. TCTL1/TCTL2 Field Descriptions

Table 7-10. Compare Result Output Action

MC9S12XDP512 Data Sheet, Rev. 2.21

Timer disconnected from output pin logic

Toggle OCx output line

Clear OCx output line to zero

Set OCx output line to one

Freescale Semiconductor