CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 1276

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics
In
In
1
1278
Num
0.5 t
Figure A-10
Table A-27
10
11
12
13
(CPOL = 0)
(CPOL = 1)
1
1
2
3
4
5
6
7
8
9
(Output)
bus
NOTE: Not defined
(Input)
(Input)
(Input)
(Input)
MISO
MOSI
SCK
SCK
added due to internal synchronization delay
SS
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
the timing characteristics for slave mode are listed.
SCK frequency
SCK period
Enable lead time
Enable lag time
Clock (SCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time (time to data active)
Slave MISO disable time
Data valid after SCK edge
Data valid after SS fall
Data hold time (outputs)
Rise and fall time inputs
Rise and fall time outputs
the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
Note
See
7
2
Characteristic
Slave
4
5
Table A-27. SPI Slave Mode Timing Characteristics
9
MSB IN
1
Figure A-10. SPI Slave Timing (CPHA = 1)
MSB OUT
6
MC9S12XDP512 Data Sheet, Rev. 2.21
4
12
12
11
Bit 6 . . . 1
Bit 6 . . . 1
Symbol
t
t
t
wsck
t
f
t
t
lead
t
vsck
t
t
t
sck
sck
t
vss
t
lag
t
dis
ho
rfo
su
hi
rfi
a
Min
DC
20
—
—
—
—
—
—
4
4
4
4
8
8
13
13
Slave LSB OUT
3
LSB IN
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29 + 0.5 t
29 + 0.5 t
Freescale Semiconductor
8
Max
1 4
20
22
—
—
—
—
—
—
8
8
bus
bus
1
1
Unit
f
t
t
t
t
bus
bus
bus
bus
bus
ns
ns
ns
ns
ns
ns
ns
ns
ns