CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 858

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.45 Port P Interrupt Flag Register (PIFP)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the
PIFP register. Writing a “0” has no effect.
860
PIFP[7:0]
Reset
Field
7–0
W
R
PIFP7
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
7
Writing a logic level “1” clears the associated flag.
PIFP6
0
6
Figure 22-47. Port P Interrupt Flag Register (PIFP)
Table 22-44. PIFP Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PIFP5
0
5
PIFP4
0
4
Description
PIFP3
0
3
PIFP2
0
2
Freescale Semiconductor
PIFP1
0
1
PIFP0
0
0