CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 630

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU)
Read: Anytime
Write: Anytime when RWPE = 0
17.4
The MMC block performs several basic functions of the S12X sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
17.4.1
630
Address: 0x011F
SHU[6:0]
Reset
•
•
•
Field
6–0
W
R
Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory
and no external accesses are allowed.
Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external
bus in this mode.
Emulation single-chip mode
Tool vendors use this mode for emulation systems in which the user’s target application is normal
single-chip mode. Code is executed from external or internal memory depending on the set-up of
the EROMON bit (see
is active in both cases to allow observation of internal operations (internal visibility).
Functional Description
MCU Operating Mode
RAM Shared Region Upper Boundary Bits 6–0 — These bits define the upper boundary of the shared
memory in multiples of 256 bytes. The block selected by this register is included in the region. See
for details.
1
1
7
Figure 17-20. RAM Shared Region Upper Boundary Register (RAMSHU)
= Unimplemented or Reserved
SHU6
1
6
Section 1.3.2.5, “MMC Control Register
Table 17-17. RAMSHU Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
SHU5
1
5
SHU4
1
4
Description
SHU3
1
3
(MMCCTL1)”). The external bus
SHU2
1
2
Freescale Semiconductor
SHU1
1
1
Figure 1-25
SHU0
1
0