CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 284

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 6 XGATE (S12XGATEV2)
TST
Operation
RS – 0
Subtracts zero from the content of register RS using binary subtraction and discards the result.
CCR Effects
Code and CPU Cycles
284
N:
Z:
V:
C:
TST RS
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & result[15]
Z
NONE (translates to SUB R0, RS, R0)
V
Source Form
C
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Mode
TRI
Test Register
0
0
0
1
1
0
Machine Code
0
0
RS1
0
0
Freescale Semiconductor
0
0
TST
0
Cycles
P

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