CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 583

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
Figure 15-7
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 16 target clock cycles.
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
Freescale Semiconductor
and
Section 15.3.2.1, “BDM Status Register (BDMSTS)”
Hardware
Hardware
Firmware
Firmware
TRACE
Read
Read
Write
Write
GO,
represents the BDM command structure. The command blocks illustrate a series of eight bit
If the bus rate of the target processor is unknown or could be changing or the
external wait function is used, it is recommended that the ACK
(acknowledge function) is used to indicate when an operation is complete.
When using ACK, the delay times are automated.
AT ~16 TC/Bit
Command
Command
Command
Command
Command
8 Bits
DELAY
48-BC
76-BC
Delay
AT ~16 TC/Bit
Figure 15-7. BDM Command Structure
Address
Address
16 Bits
MC9S12XDP512 Data Sheet, Rev. 2.21
Data
Command
Next
Data
DELAY
36-BC
NOTE
for information on how serial clock rate is selected.
150-BC
Delay
Command
Command
Next
Next
Data
Chapter 15 Background Debug Module (S12XBDMV2)
AT ~16 TC/Bit
16 Bits
Data
BC = Bus Clock Cycles
TC = Target Clock Cycles
Section 15.4.6, “BDM Serial Interface”
150-BC
Delay
1
Command
Command
Next
Next
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