CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 558

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 14 Voltage Regulator (S12VREG3V3V5)

PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors

(220 nF, X7R ceramic).

In Shutdown Mode, an external supply driving V

This optional signal is used to shutdown VREG_3V3. In that case, V

provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the

VREG_3V3 is either in Full Performance Mode or in Reduced Power Mode.

For the connectivity of VREGEN, see device speciﬁcation.

This section provides a detailed description of all registers accessible in VREG_3V3.

If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within

it’s memory slice.

Memory Map and Register Deﬁnition

provides an overview of all used registers.

VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins

Module Memory Map

is not supported while MCU is powered.

Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa

are the secondary outputs of VREG_3V3 that provide the power supply for the

Autonomous Periodical Interrupt Trimming Register (VREGAPITR)

Optional Regulator Enable Pin

Autonomous Periodical Interrupt Control Register (VREGAPICL)

Autonomous Periodical Interrupt Period High (VREGAPIRH)

Autonomous Periodical Interrupt Period Low (VREGAPIRL)

MC9S12XDP512 Data Sheet, Rev. 2.21

HT Control Register (VREGHTCL)

Control Register (VREGCTRL)

Table 14-2. Memory Map

can replace the voltage regulator.

Freescale Semiconductor