CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 838

Manufacturer Part Number

CSM9S12XDT512SLK

KIT STUDENT LEARNING 16BIT

Manufacturer

Freescale Semiconductor

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

22.3.2.17 Port T Data Register (PTT)

Read: Anytime.

Write: Anytime.

22.3.2.18 Port T Input Register (PTIT)

Read: Anytime.

Write: Never, writes to this register have no effect.

These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated

Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used

with the ECT, these pins can be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

Port T Input — This register always reads back the buffered state of the associated pins. This can also be used

to detect overload or short circuit conditions on output pins.

= Unimplemented or Reserved

Figure 22-20. Port T Input Register (PTIT)

Figure 22-19. Port T Data Register (PTT)

Table 22-22. PTIT Field Descriptions

Table 22-21. PTT Field Descriptions

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor