CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 623

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.2.5
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for
XGATE). Both local and global memory maps are affected.
Freescale Semiconductor
Address: 0x0013 PRR
EROMON
ROMHM
ROMON
Reset
Field
2
1
0
W
R
Enables emulated Flash or ROM memory in the memory map
Write: Never
0 Disables the emulated Flash or ROM in the memory map.
1 Enables the emulated Flash or ROM in the memory map.
FLASH or ROM only in higher Half of Memory Map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Enable FLASH or ROM in the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the memory map.
MMC Control Register (MMCCTL1)
0
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
$4000–$7FFF will be mapped to $7F_4000-$7F_7FFF in the global memory space.
Flash or ROM can still be accessed through the program page window. Accesses to $4000–$7FFF will be
mapped to $14_4000-$14_7FFF in the global memory space (external access).
= Unimplemented or Reserved
0
0
6
Figure 17-10. MMC Control Register (MMCCTL1)
Table 17-9. MMCCTL1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
CAUTION
0
0
4
Description
0
0
3
Chapter 17 Memory Mapping Control (S12XMMCV2)
EROMCTL
EROMON
2
ROMHM
0
1
ROMCTL
ROMON
0
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