CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 818

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2
Table 22-3
(IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1
2
820
Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
Applicable only on Port P, H, and J.
DDR
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
summarizes the effect on the various configuration bits, data direction (DDR), output level
IO
Register Descriptions
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
All register bits in this module are completely synchronous to internal
clocks during a register read.
RDR
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
Table 22-3. Pin Configuration Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
PS
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
1
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
NOTE
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Function
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Freescale Semiconductor
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt