CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 969

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PJ2
PJ0
Pin
1. Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details.
23.0.10 Low-Power Options
23.0.10.1 Run Mode
No low-power options exist for this module in run mode.
23.0.10.2 Wait Mode
No low-power options exist for this module in wait mode.
23.0.10.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H,
and J.
Initialization and Application Information
Normal Single-
It is not recommended to write PORTx and DDRx in a word access. When changing the
register pins from inputs to outputs, the data may have extra transitions during the write
access. Initialize the port data register before enabling the outputs.
Power consumption will increase the more the voltages on general purpose input pins
deviate from the supply voltages towards mid-range because the digital input buffers
operate in the linear region.
Table 23-70. Expanded Bus Pin Functions versus Operating Modes (continued)
GPIO
GPIO
Chip
Single-Chip Modes
Special Single-
GPIO
GPIO
Chip
Expanded
Normal
GPIO
GPIO
CS1
CS3
or
or
Single-Chip
Emulation
GPIO
GPIO
Expanded Modes
Emulation
Expanded
GPIO
GPIO
CS1
CS3
or
or
Special
GPIO
GPIO
Test
CS1
CS3
or
or

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