CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 973

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24
DG128 Port Integration Module (S12XDG128PIMV2)
Introduction
The S12XD family port integration module (below referred to as PIM) establishes the interface between
the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the
I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers the description of:
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices. Interrupts can be enabled on specific pins resulting in status flags.
The I/O’s of 2 MSCAN and 2 SPI modules can be routed from their default location to alternative port
pins.
24.0.1
A full-featured PIM module includes these distinctive registers:
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Port A, B
Port E associated with the IRQ, XIRQ interrupt inputs
Port K
Port T connected to the Enhanced Capture Timer (ECT) module
Port S associated with 2 SCI and 1 SPI modules
Port M associated with 2 MSCAN modules and 1 SCI module
Port P connected to the PWM and 1 SPI module — inputs can be used as an external interrupt
source
Port H associated with 2 SCI modules — inputs can be used as an external interrupt source
Port J associated with 1 MSCAN, 1 SCI, and 1 IIC module — inputs can be used as an external
interrupt source
Port AD1 associated with one 16-channel ATD module
Features
The implementation of the PIM is device dependent. Therefore some
functions are not available on certain derivatives or80-pin package options.
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
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