FX1S-30MR-ES/UL MITSUBISHI, FX1S-30MR-ES/UL Datasheet - Page 222

• Manufacturer Part Number: FX1S-30MR-ES/UL
• Description: PLC, 16 IN, 14 RELAY OUT, 110V/2
• Manufacturer: MITSUBISHI

Specifications of FX1S-30MR-ES/UL

• No. Of Analogue Inputs: 16
• No. Of Analogue Outputs: 14
• Ip/nema Rating: IP10
• Approval Bodies: CE, CUL, UL
• External Depth: 49mm
• External Length / Height: 90mm
• External Width: 60mm
• Mounting Type: Panel

5.9.5
FX Series Programmable Controlers
CCD (FNC 84)
Points to note:
a) The SUM of the data stack is stored at destination D while the Parity for the data stack is
b) During the Parity check an even result is indicated by the use of a 0 (zero) while an odd
c) This instruction can be used with the 8 bit/ 16 bit mode flag M8161. The following results will
It should be noted that when M8161 is OFF ‘n’ represents the number of consecutive bytes
checked by the CCD instruction. When M8161 is ON only the lower bytes of ‘n’ consecutive
words are used.
The ‘SUM’ is quite simply a summation of the total quantity of data in the data stack. The Parity
is checked vertically through the data stack as shown by the shaded areas.
CCD
FNC 84
(Check
Code)
Mnemonic
stored at D
parity is indicated by a 1 (one).
occur under these circumstances. See page 10-20 for more details about M8161.
D100
D101
D102
SUM D0
Vertical
Sourse (S)
party
D1
H
L
H
L
H
L
FF
FF
FF
00
F0
0F
+1
Checks the
‘vertical’ parity of
a data stack
1
1
1
0
1
0
0
M8161=OFF
.
Function
1
1
1
0
1
0
0
1
1
1
0
1
0
0
Bit patterm
3FC
1
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
0
1
0
KnX, KnY,
KnM,
KnS
T, C, D
1
1
1
0
0
1
0
1
1
1
0
0
1
0
S
Operation:
This instruction looks at a byte (8 bit) stack of data
from head address (S)for n bytes and checks the
vertical bit pattern for parity and sums the total
data stack. These two pieces of data are then
stored at the destination (D).
KnY, KnM, KnS
T, C, D
Operands
D100 L
D101 L
D102 L
D103 L
D104 L
D105 L
SUM D0
Vertical
Sourse (S)
party
D1
D
FF
0F
F0
F0
0F
00
1
0
0
1
1
0
1
K, H
D
Note:
n = 1 to 256
M8161=ON
1
0
0
1
1
0
1
n
1
0
0
1
1
0
1
Bit patterm
2FD
1
0
0
1
1
0
1
Applied Instructions 5
1
0
1
0
0
1
1
CCD,
CCDP:
7 steps
Program steps
1
0
1
0
0
1
1
5-100
1
0
1
0
0
1
1
1
0
1
0
0
1
1