EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 114

EP2AGX95EF29I5N

Manufacturer Part Number

EP2AGX95EF29I5N

Description

IC ARRIA II GX FPGA 95K 780FBGA

Manufacturer

Altera

Series

Arria II GXr

Datasheets

1.EP2AGX45CU17C6N.pdf (96 pages)

2.EP2AGX45CU17C6N.pdf (14 pages)

3.EP2AGX45CU17C6N.pdf (692 pages)

4.EP2AGX45CU17C6N.pdf (10 pages)

5.EP2AGX45CU17C6N.pdf (88 pages)

6.EP2AGX95EF29I5N.pdf (306 pages)

Specifications of EP2AGX95EF29I5N

Number Of Logic Elements/cells

89178

Number Of Labs/clbs

3747

Total Ram Bits

6679

Number Of I /o

372

Voltage - Supply

0.87 V ~ 0.93 V

Mounting Type

Surface Mount

Operating Temperature

-40°C ~ 100°C

Package / Case

780-FBGA

Family Name

Arria® II GX

Number Of Logic Blocks/elements

93674

# I/os (max)

372

Frequency (max)

500MHz

Operating Supply Voltage (typ)

900mV

Logic Cells

93674

Ram Bits

7025459.2

Operating Supply Voltage (min)

0.87V

Operating Supply Voltage (max)

0.93V

Operating Temp Range

-40C to 100C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

780

Package Type

FC-FBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

Lead Free Status / Rohs Status

Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

EP2AGX95EF29I5N

Manufacturer:

Altera

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

EP2AGX95EF29I5N

Manufacturer:

ALTERA

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5–10

Table 5–4. Clock Input Pin Connectivity to RCLK Networks for Arria II GX Devices

Table 5–5. Clock Input Pin Connectivity to the RCLK Networks for Arria II GZ Devices

Arria II Device Handbook Volume 1: Device Interfaces and Integration

RCLK [12, 14, 16, 18, 20, 22]

RCLK [13, 15, 17, 19, 21, 23]

RCLK [24..35]

RCLK [36, 38, 40, 42, 44, 46]

RCLK [37, 39, 41, 43, 45, 47]

RCLK [0, 4, 6, 10]

RCLK [1, 5, 7, 11]

RCLK [2, 8]

RCLK [3, 9]

RCLK [13, 17, 21, 23,

27, 31]

RCLK [12, 16, 20, 22,

26, 30]

RCLK [15, 19, 25, 29]

RCLK [14, 18, 24, 28]

RCLK [35, 41]

RCLK [34, 40]

RCLK [33, 37, 39, 43]

RCLK [32, 36, 38, 42]

RCLK [47, 51, 57, 61]

RCLK [46, 50, 56, 60]

RCLK [45, 49, 53, 55,

59, 63]

RCLK [44, 48, 52, 54,

58, 62]

Clock Resource

Table 5–4

and RCLKs in Arria II devices. A given clock input pin can drive two adjacent RCLK

networks to create a dual-RCLK network.

—

and

—

Table 5–5

—

v —

—

v —

list the connectivity between the dedicated clock input pins

—

CLK (p/n Pins)

—

Chapter 5: Clock Networks and PLLs in Arria II Devices

—

CLK (p/n Pins)

—

December 2010 Altera Corporation

Clock Networks in Arria II Devices

—

v —

—

EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 114

EP2AGX95EF29I5N

Specifications of EP2AGX95EF29I5N

Available stocks

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