EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 77
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Arria II Devices
Simplified DSP Operation
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
December 2010 Altera Corporation
Input
Data
144
Half-DSP Block
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time and P[36..0] are the results from the
two-multiplier adder units.
Equation 4–2
(four-multiplier adder), and
operation, but with a maximum of a 44-bit accumulation capability by feeding the
output from the output register bank back to the adder/accumulator block, as shown
in
You can bypass all register stages depending on which mode you select, except
accumulation and loopback mode. In these two modes, you must enable at least one
set of the registers. If the register is not enabled, an infinite loop occurs.
To support FIR-like structures efficiently, a major addition to the DSP block in Arria II
devices is the ability to propagate the result of one half block to the next half block
completely in the DSP block without additional soft logic overhead. This is achieved
by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of
a previous half block with the 44-bit result of the current block. The 44-bit result is
either fed to the next half block or out of the DSP block with the output register stage
shown in
Figure
W
4–3.
Figure
n
[43..0] = W
provides a sum of four 18 × 18-bit multiplication operations
4–4. Detailed examples are described in later sections.
n-1
[43..0] ± Z
Equation 4–3
n
[37..0]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
provides a four 18 × 18-bit multiplication
44
Result[]
4–5
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