EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 508
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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2–18
Arria II Device Handbook Volume 2: Transceivers
Receiver Channel Datapath Clocking
f
This section describes receiver PMA and PCS datapath clocking in supported
configurations. The receiver datapath clocking varies between non-bonded and
bonded channel configurations. It also varies with the use of PCS blocks; for example,
deskew FIFO and rate matcher.
Non-Bonded Channel Configurations
In non-bonded channel configurations, the receiver PCS blocks of each channel are
clocked independently. Each non-bonded channel also has separate rx_analogreset
and rx_digitalreset signals that allow independent reset of the receiver PCS logic in
each channel.
For more information about transceiver reset and power-down signals, refer to the
Reset Control and Power Down in Arria II Devices
In addition, using the rate matcher block affects PCS clocking in non-bonded channel
configurations.
Non-Bonded Receiver Clocking Without Rate Matcher
The following functional modes have non-bonded receiver channel configuration
without rate-matcher:
■
■
■
■
■
Serial RapidIO
SONET/SDH
SDI
CPRI/OBSAI
Basic without rate matcher
chapter.
Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
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