EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 348
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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9–68
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Table 9–27
both for volatile key and non-volatile key programming.
Table 9–27. Design Security Configuration Schemes Availability
You can use the design security feature with other configuration features, such as the
compression and remote system upgrade features. When you use compression with
the design security feature, the configuration file is first compressed and then
encrypted using the Quartus II software. During configuration, the Arria II device
first decrypts and then decompresses the configuration file.
FPP
AS
Fast AS
PS
JTAG
Notes to
(1) In this mode, the host system must send a DCLK that is ×4 the data rate.
(2) JTAG configuration supports only unencrypted configuration file.
Configuration Scheme
(2)
Table
lists the configuration schemes that support the design security feature
9–27:
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
MAX II device or microprocessor and flash memory
Serial configuration device
Serial configuration device
MAX II device or microprocessor and flash memory
Download cable
MAX II device or microprocessor and flash memory
Download cable
Configuration Method
December 2010 Altera Corporation
Design Security
Security
v
Design
v
v
v
v
—
—
(1)
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