EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 469
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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- Download datasheet (22Mb)
Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–78. Deskew FIFO–Lane Skew at the Receiver Input
December 2010 Altera Corporation
Lane 0
Lane 2
K
Lane 1
Lane 3
K
K
Lane 0
Lane 1
Lane 2
Lane 3
R
K
K
K
Figure 1–78
/A/ code group to align the channels.
After alignment of the first ||A|| column, if three additional aligned ||A|| columns are
observed at the output of the deskew FIFOs of the four channels, the
rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at the
output of the deskew FIFOs in all four channels with no aligned ||A|| columns in
between, the rx_channelaligned signal is de-asserted low, indicating loss of channel
alignment.
Rate Match FIFO in XAUI Mode
In XAUI mode, the rate match FIFO is capable of compensating up to ±100 PPM
(200 PPM total) difference between the upstream transmitter and the local receiver
reference clock. The XAUI protocol requires the transmitter to send /R/ (/K28.0/)
code groups simultaneously on all four lanes (denoted as the ||R|| column) during
inter-packet gaps, adhering to rules listed in the IEEE P802.3ae specification.
The rate match operation begins after rx_syncstatus and rx_channelaligned are
asserted. The rx_syncstatus signal is from the word aligner, indicating that
synchronization is acquired on all four channels; the rx_channelaligned signal is
from the deskew FIFO, indicating channel alignment.
The rate match FIFO looks for the ||R|| column (simultaneous /R/ code groups on all
four channels) and deletes or inserts ||R|| columns to prevent the rate match FIFO
from overflowing or underrunning. The rate match FIFO can insert or delete as many
||R|| columns as necessary to perform the rate match operation.
The rx_rmfifodatadeleted and rx_rmfifodatainserted flags indicate rate match
FIFO deletion and insertion events, respectively, and are forwarded to the FPGA
fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each of the four
channels goes high for one clock cycle per deleted ||R|| column. If an ||R|| column is
inserted, the rx_rmfifoinserted flag from each of the four channels goes high for one
clock cycle per inserted ||R|| column.
K
K
K
K
A
K
R
K
K
K
K
K
K
R
A
R
R
R
R
R
shows lane skew at the receiver input and how the deskew FIFO uses the
R
A
K
A
A
A
A
A
R
K
R
K
K
K
K
K
K
R
R
R
R
R
R
R
R
R
K
K
R
R
R
R
R
K
K
K
K
K
K
K
K
K
R
K
K
K
K
K
R
R
R
K
R
R
R
R
K
R
K
Arria II Device Handbook Volume 2: Transceivers
K
K
K
K
R
R
R
R
R
R
Lanes Skew at
Receiver Input
Lanes are Deskewed by Aligning
the /A/ Code Groups
1–83
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