EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 52
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
- Current page: 52 of 692
- Download datasheet (22Mb)
3–6
Figure 3–4. Address Clock Enable During Read Cycle Waveform
Arria II Device Handbook Volume 1: Device Interfaces and Integration
rdaddress
rden
addressstall
latched address
(inside memory)
q (synch)
q (asynch)
inclock
Figure 3–3
addressstall refers to the address clock enable.
Figure 3–3. Address Clock Enable
Figure 3–4
doutn-1
doutn
shows an address clock enable block diagram. The port name
shows the address clock enable waveform during the read cycle.
an
a0
addressstall
address[0]
address[N]
doutn
a0
dout0
clock
a1
dout0
a2
1
0
1
0
a1
dout1
a3
address[N]
address[0]
register
register
dout1
a4
Chapter 3: Memory Blocks in Arria II Devices
a4
dout4
address[N]
a5
address[0]
December 2010 Altera Corporation
dout4
a5
dout5
a6
Memory Features
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