EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 529
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–10. Transmitter Phase Compensation FIFO Read Clocks for Arria II Devices
December 2010 Altera Corporation
Non-Bonded Channel Configuration
×4 Bonded Channel Configuration
×8 Bonded Channel Configuration
Configuration
1
1
1
Table 2–10
Quartus II software selects in various configurations.
To ensure that you understand the 0 PPM clock driver rule, the Quartus II software
expects the “GXB 0 PPM Core Clock Setting” user assignment whenever you use the
tx_coreclk port to drive the transmitter phase compensation FIFO write clock.
Failure to make this assignment when using the tx_coreclk port results in a
Quartus II compilation error.
GXB 0 PPM Core Clock Setting
The GXB 0 PPM core clock setting is intended for advanced users who know the
clocking configuration of the entire system and want to reduce the FPGA fabric global
and regional clock resource utilization. The GXB 0 PPM core clock setting allows the
following clock drivers to drive the tx_coreclk ports:
■
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in the FPGA
logic to drive the tx_coreclk ports.
Because the GXB 0 PPM core clock setting allows FPGA CLK input pins and
transceiver REFCLK pins as the clock driver, the Quartus II compiler cannot determine
if there is a 0 PPM difference between the FIFO write clock and read clock for each
channel.
You must ensure that the clock driver for all connected tx_coreclk ports has a 0 PPM
difference with respect to the FIFO read clock in those channels.
tx_clkout in non-bonded channel configurations
coreclkout in bonded channel configurations
FPGA CLK input pins
Transceiver REFCLK pins
Clock output from the left-corner PLLs (PLL_1 and PLL_4)
lists the transmitter phase compensation FIFO read clocks that the
Parallel transmitter PCS clock from the
local clock divider in the associated
channel (tx_clkout)
Low-speed parallel clock from the CMU0
clock divider of the associated
transceiver block (coreclkout)
Low-speed parallel clock from the CMU0
clock divider of the master transceiver
block (coreclkout from master
transceiver block)
Without Byte Serializer
Transmitter Phase Compensation FIFO Read Clock
Arria II Device Handbook Volume 2: Transceivers
Divide-by-two version of the parallel
transmitter PCS clock from the local
clock divider in the associated channel
(tx_clkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the associated transceiver
block (coreclkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the master transceiver block
(coreclkout from master transceiver
block)
With Byte Serializer
2–39
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