EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 69
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
- Current page: 69 of 692
- Download datasheet (22Mb)
Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
Figure 3–23. MLABs Mixed-Port Read-During-Write: Old Data Mode
Figure 3–24. MLABs Mixed-Port Read-During-Write: Don’t Care Mode
December 2010 Altera Corporation
q_b(registered)
q_b(registered)
1
byteena_a
wraddress
rdaddress
byteena_a
wraddress
rdaddress
data_in
wrena
data_in
clk_a
wrena
clk_a
Read-during-write behavior is controlled using the RAM MegaWizard Plug-In
Manager. For more information about how to implement the desired behavior, refer to
the
Figure 3–23
behavior for old data mode in MLABs.
Figure 3–24
behavior for don’t care mode in MLABs.
Internal Memory (RAM and ROM) Megafunction User
AAAA
shows a sample functional waveform of mixed-port read-during-write
shows a sample functional waveform of mixed-port read-during-write
AAAA
11
11
A0 (old data)
A0
A0
A0
A0
AAAA
BBBB
01
BBBB
01
AAAA
AABB
CCCC
10
CCCC
10
Arria II Device Handbook Volume 1: Device Interfaces and Integration
AABB
DDDD
DDDD
CCBB
11
11
A1(old data)
DDDD
EEEE
A1
A1
EEEE
A1
A1
01
01
Guide.
DDDD
FFFF
DDEE
FFFF
10
10
DDEE
FFEE
3–23
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