EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 368
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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11–8
Document Revision History
Table 11–6. Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
July 2010
November 2009
February 2009
Date
Version
Table 11–6
4.0
2.0
3.0
1.0
■
■
■
■
■
■
Updated for Arria II GX v10.0 release:
■
■
Updated for Arria II GX v9.1 release:
■
■
■
Initial release.
Updated for the Quartus II software version 10.1 release.
Added Arria II GZ devices information.
Added
Circuitry”
Added
Updated
Minor text edits.
Updated “BST Operation Control” section.
Minor text edits.
Updated Table 11–1 and Table 11–2.
Updated “I/O Voltage Support in a JTAG Chain” section.
Minor text edits.
lists the revision history for this document.
“BST Architecture for Arria II Devices”
Table 11–3
Table 11–1
and
and
Table 11–5
Table 11–2
Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
Changes
and
“Disabling IEEE Std. 1149.1 BST
December 2010 Altera Corporation
Document Revision History
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