EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 127
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–18. External Clock Outputs for Top and Bottom PLLs in Arria II GZ Devices
Notes to
(1) You can feed these clock output pins using any one of the C[9..0], or m counters.
(2) The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. The CLKOUT1 and CLKOUT2 pins are
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
December 2010 Altera Corporation
dual-purpose I/O pins that you can use as two single-ended outputs or one differential external feedback input pin. The CLKOUT3 and CLKOUT4
pins are two single-ended output pins.
Figure
Top/Bottom
PLLs
5–18:
PLL_<#>_CLKOUT0p (1), (2)
clkena0 (3)
clkena1 (3)
m(fbout)
Figure 5–18
For Arria II GZ devices, any of the output counters (C[9..0] on the top and bottom
PLLs and C[6..0] on the left and right PLLs) or the M counter can feed the dedicated
external clock outputs, as shown in
counter or frequency can drive all output pins available from a given PLL. Each left
and right PLL supports two clock I/O pins, configured as either two single-ended
I/Os or one differential I/O pair. When using both pins as single-ended I/Os, one of
them can be the clock output while the other pin is the external feedback input (FB)
pin. Therefore, for single-ended I/O standards, the left and right PLLs only support
external feedback mode.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
PLL_<#>_CLKOUT0n (1), (2)
shows the clock I/O pins associated with the top and bottom PLLs.
PLL_<#>_FBp/CLKOUT1 (1), (2)
clkena3 (3)
clkena2 (3)
PLL_<#>_FBn/CLKOUT2 (1), (2)
Figure 5–18
Arria II Device Handbook Volume 1: Device Interfaces and Integration
clkena4 (3)
and
clkena5 (3)
Figure
PLL_<#>_CLKOUT3
(1), (2)
5–19. Therefore, one
PLL_<#>_CLKOUT4
(1), (2)
Internal Logic
5–23
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