EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 449

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Table 1–15. Supported Features in PCIe Mode for Arria II Devices (Part 1 of 2)
December 2010 Altera Corporation
×1, ×4, ×8 link configurations
PCIe-compliant synchronization state machine
±300 PPM (total 600 PPM) clock rate compensation
8-bit FPGA fabric-transceiver interface
16-bit FPGA fabric-transceiver interface
Transmitter buffer electrical idle
Receiver detection
8B/10B encoder disparity control when transmitting compliance pattern
Power state management
Receiver status encoding
f
f
For descriptions of PCIe hard IP architecture and PCIe mode configurations allowed
when using the PCIe hard IP block, refer to the
For more information about transceiver datapath clocking in different PCIe
configurations, refer to the
The transmitter datapath in PCIe mode consists of the:
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The receiver datapath in PCIe mode consists of the:
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Table 1–15
Gen2 (5.0 Gbps) data rate configurations.
PIPE interface
TX phase compensation FIFO
Optional byte serializer (enabled for 16-bit and disabled for 8-bit FPGA
fabric-transceiver interface)
8B/10B encoder
10:1 serializer
Transmitter buffer with receiver detect circuitry
Receiver input buffer with signal detect circuitry
1:10 deserializer
Word aligner that implements PCIe-compliant synchronization state machine
Optional rate match FIFO (clock rate compensation) that can tolerate up to
600 PPM frequency difference
8B/10B decoder
Optional byte deserializer (enabled for 16-bit and disabled for 8-bit FPGA
fabric-transceiver interface)
RX phase compensation FIFO
PIPE interface
Feature
lists features supported in PCIe functional mode for Gen1 (2.5 Gbps) and
Transceiver Clocking in Arria II Devices
PCI Express Compiler User
2.5 Gbps (Gen1)
Arria II Device Handbook Volume 2: Transceivers
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chapter.
5.0 Gbps (Gen2)
Only ×1 and ×4 are
supported
Guide.
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