EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 94

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–22
Arria II Device Handbook Volume 1: Device Interfaces and Integration
18 × 18 Complex Multiplier
You can configure the DSP block to implement complex multipliers with the
two-multiplier adder mode. A single half-DSP block can implement one 18-bit
complex multiplier.
Equation 4–4
Equation 4–4. Complex Multiplication Equation
To implement this complex multiplication in the DSP block, the real part
[(a × c) – (b × d)] is implemented with two multipliers feeding one subtractor block,
and the imaginary part [(a × d) + (b × c)] is implemented with another two multipliers
feeding an adder block. This mode automatically assumes all inputs are using signed
numbers.
Figure 4–15
assumes all inputs are using signed numbers.
Figure 4–15. Complex Multiplier Using Two-Multiplier Adder Mode
C
D
A
B
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j[(a × d) + (b × c)]
clock[3..0]
shows an 18-bit complex multiplication. This mode automatically
ena[3..0]
aclr[3..0]
shows how you can write a complex multiplication.
Half-DSP Block
signa
signb
+
-
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
December 2010 Altera Corporation
36
36
(A × D) + (B × C)
(Imaginary Part)
(A × C) - (B × D)
(Real Part)