EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 344

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II Design Security Solution
Arria II devices are SRAM-based devices. To provide design security, Arria II devices
require a 256-bit security key for configuration bitstream encryption.
To carry out secure configuration, follow these steps (refer to
1. Program the security key into the Arria II device.
2. Encrypt the configuration file and store it in the external memory.
3. Configure the Arria II device.
At system power-up, the external memory device sends the encrypted configuration
file to the Arria II device.
Figure 9–29. Design Security
Note to
(1) Step 1, Step 2, and Step 3 correspond to the procedure described in
Program the user-defined 256-bit AES keys to the Arria II device through the JTAG
interface.
Encrypt the configuration file with the same 256-bit keys used to program the
Arria II device. Encryption of the configuration file is done using the Quartus II
software. The encrypted configuration file is then loaded into the external
memory, such as a configuration or flash device.
Figure
9–29:
User-Defined
Configuration
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Encrypted
AES Key
File
(Note 1)
Step 2
Step 1
“Design Security” on page
Configuration
Arria II FPGA
Memory or
Key Storage
Decryption
December 2010 Altera Corporation
Device
AES
Figure
Step 3
9–29):
9–61.
Design Security