EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 245
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Locations of the I/O Banks
Table 8–1. LVDS Channels Supported in Arria II GX Device Row I/O Banks
Table 8–2. LVDS Channels Supported in Arria II GX Device Column I/O Banks
2)
December 2010 Altera Corporation
Notes to
(1) Dedicated SERDES and DPA circuitry only exist on the right side of the device in the Row I/O banks.
(2) R
(3) Rx = True LVDS input buffers without R
(4) Tx = True LVDS output buffers and dedicated SERDES transmitter channel.
(5) eTx = Emulated LVDS output buffers, either LVDS_E_3R or LVDS_E_1R.
(6) The LVDS channel count does not include dedicated clock input pins and PLL clock output pins.
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX125
EP2AGX190
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX45
EP2AGX65
EP2AGX95
Device
Device
D
= True LVDS input buffers with R
Table
8–1:
1
358-Pin FlipChip UBGA
358-Pin FlipChip UBGA
8(Rx, Tx, or eTx)
8(Rx, Tx or eTx)
24(Rx, Tx, or eTx)
24(Rx, Tx, or eTx)
8(R
8(R
25(R
25(R
Dedicated SERDES and DPA circuitry are only available on the right side of the device
in row I/O banks. SERDES with DPA receivers are only available on differential pins
in the row I/O banks and SERDES transmitters are only available on transmit (Tx)
pins in the row I/O banks. The receive (Rx) pins in row I/O banks are receiver
channels without dedicated SERDES and DPA circuitry.
D
D
or eTx) +
or eTx) +
D
D
—
—
—
—
or eTx) +
or eTx) +
—
—
—
D
OCT support and dedicated SERDES receiver channel with DPA circuitry.
D
OCT support and dedicated SERDES receiver channel with DPA circuitry.
572-Pin FlipChip FBGA
24(Rx, Tx, or eTx)
24(Rx, Tx, or eTx)
24(Rx, Tx or eTx)
24(Rx, Tx or eTx)
572-Pin FlipChip FBGA
24(R
24(R
24(R
24(R
32(Rx, Tx, or eTx)
32(Rx, Tx, or eTx)
32(Rx, Tx, or eTx)
32(Rx, Tx, or eTx)
33(R
33(R
33(R
33(R
D
D
D
D
—
—
or eTx) +
or eTx) +
or eTx) +
or eTx) +
D
D
D
D
or eTx) +
or eTx) +
or eTx) +
or eTx) +
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
780-Pin FlipChip FBGA
28((Rx, Tx or eTx)
28(Rx, Tx, or eTx)
780-Pin FlipChip FBGA
28(Rx, Tx or eTx)
28(Rx, Tx or eTx)
28(Rx, Tx or eTx)
28(Rx, Tx or eTx)
(Note
28(R
28(R
28(R
28(R
28(R
28(R
56(Rx, Tx, or eTx)
56(Rx, Tx, or eTx)
56(Rx, Tx, or eTx)
56(Rx, Tx, or eTx)
56(Rx, Tx, or eTx)
57(R
57(R
57(R
57(R
57(R
(Note
D
D
D
D
D
D
1), (2), (3), (4), (5),
or eTx) +
or eTx) +
or eTx) +
or eTx) +
or eTx) +
or eTx)+
D
D
D
D
D
or eTx) +
or eTx) +
or eTx) +
or eTx) +
or eTx) +
1), (2), (3), (4), (5),
1152-Pin FlipChip FBGA
1152-Pin FlipChip FBGA
32(Rx, Tx, or eTx)
32(Rx, Tx or eTx)
48(Rx, Tx or eTx)
48(Rx, Tx or eTx)
(6)
32(R
32(R
48(R
48(R
72(Rx, Tx, or eTx)
72(Rx, Tx, or eTx)
96(Rx, Tx, or eTx)
73(R
73(R
97(R
(6)
D
D
D
D
—
—
or eTx) +
or eTx) +
or eTx) +
or eTx) +
(Part 1 of
D
D
D
—
—
or eTx) +
or eTx) +
or eTx) +
8–5
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