EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 475
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
- Current page: 475 of 692
- Download datasheet (22Mb)
Chapter 1: Transceiver Architecture in Arria II Devices
Test Modes
Figure 1–85. Enabled PCS Functional Blocks in Parallel Loopback
December 2010 Altera Corporation
Fabric
FPGA
Pattern Generator
BIST Incremental
Figure 1–85
BIST mode allows you to verify the complete PCS blocks for both the transmitter and
receiver channel. This mode is available only with a built-in 16-bit incremental pattern
generator and verifier; therefore, you must set the channel width to 16 bits in this
mode. The incremental pattern 00-FF is looped back to the receiver channel at the PCS
functional block boundary before the PMA and is sent out to the tx_dataout port.
The received data is verified by the verifier, but is not available in the FPGA fabric.
The V
V
OD
settings.
OD
BIST Incremental
Pattern Verifier
of the transmitted serial data on the tx_dataout port is based on the selected
Compensation
wrclk
shows the datapath for the BIST mode.
tx_clkout
TX Phase
FIFO
rdclk
/2
wrclk
Byte Serializer
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
8B/10B Encoder
Arria II Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Parallel Recovery Clock
Transmitter Channel
Receiver Channel
High-Speed
Serial Clock
PMA
PMA
1–89
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