EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 509

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–13. Receiver Datapath Clocking in Non-Bonded Configurations without Rate Matcher
Note to
(1) In Arria II GX and GZ devices, there is only one dedicated PCIe hard IP, which supports PCIe Gen 1 ×1, ×4, and ×8; and PCIe Gen 2 ×1 and ×4.
December 2010 Altera Corporation
Fabric
FPGA
Figure
2–13:
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
(1)
Figure 2–13
without rate matcher.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
rx_clkout[3]
rx_clkout[2]
rx_clkout[1]
rx_clkout[0]
shows receiver datapath clocking in non-bonded channel configurations
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
/2
/2
/2
/2
Arria II Device Handbook Volume 2: Transceivers
Parallel Recovered Clock
FPGA Fabric-Transceiver Interface Clock
Serial Recovered Clock
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
Clock
Clock
Clock
Clock
Input
Input
Input
Input
2–19