EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 294

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–14
Figure 9–3. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Arria II Device Handbook Volume 1: Device Interfaces and Integration
For Arria II GZ devices, use the V
external host. Altera recommends powering up the configuration system I/Os with V
Table 9–6 on page
(MAX II Device or
Microprocessor)
Figure
External Host
ADDR DATA[7..0]
Memory
9–3:
f
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
V
If a system has multiple devices that contain the same configuration data, tie all
device nCE inputs to GND and leave the nCEO pins floating. All other configuration
pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every
device in the chain. Configuration signals may require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time.
Figure 9–3
receiving the same configuration data.
You can use a single configuration chain to configure Arria II devices with other
Altera devices that support FPP configuration. To ensure that all devices in the chain
complete configuration at the same time, or that an error flagged by one device
initiates reconfiguration in all devices, tie all of the device CONF_DONE and nSTATUS
pins together.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
CCIO
/V
(1)
10 kΩ
CCPGM
CCPGM
V
CCIO
shows a multi-device FPP configuration when both Arria II devices are
pin. V
/V
(1)
CCPGM
10 kΩ
CCIO
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
/V
CCPGM
GND
must be high enough to meet the V
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Arria II Device 1
Configuring Mixed Altera FPGA Chains
MSEL[n..0]
nCEO
Table 9–7 on page
CCIO
N.C.
(2)
/V
CCPGM
IH
specification of the I/O on both the device and the
.
9–10.
December 2010 Altera Corporation
GND
Fast Passive Parallel Configuration
nCE
CONF_DONE
nSTATUS
DATA[7..0]
nCONFIG
DCLK
Arria II Device 2
chapter in
MSEL[n..0]
nCEO
CCIO
N.C.
pin.
(2)