EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 532
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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2–42
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric-Receiver Interface Clocking
The receiver phase compensation FIFO compensates for the phase difference between
the parallel receiver PCS clock (FIFO write clock) and the FPGA fabric clock (FIFO
read clock). The receiver phase compensation FIFO read clock forms the FPGA
fabric-receiver interface clock. The FIFO write and read clocks must have exactly the
same frequency, in other words, 0 PPM frequency difference.
Arria II GX and GZ transceivers provide the following two options for selecting the
receiver phase compensation FIFO read clock:
■
■
Quartus II Software-Selected Receiver Phase Compensation FIFO Read Clock
If you do not select the rx_coreclk port in the ALTGX MegaWizard Plug-In Manager,
the Quartus II software automatically selects the receiver phase compensation FIFO
read clock for each channel in that ALTGX instance. The Quartus II software selects
the FIFO read clock depending on the channel configuration.
Non-Bonded Channel Configuration with Rate Matcher
In the non-bonded channel configuration, the transceiver channels may or may not be
identical. Identical transceiver channels are defined as channels that have the same
CMU PLL and receiver CDR input reference clock source, have exactly the same CMU
PLL and receiver CDR configuration, and have exactly the same PMA and PCS
configuration.
Quartus II software-selected receiver phase compensation FIFO read clock
User-selected receiver phase compensation FIFO read clock
If all four channels within a transceiver block are identical, the Quartus II software
automatically drives the read port of the receiver phase compensation FIFO in all
four channels with tx_clkout[0], as shown in
signal to latch the receiver data and status signals from all four channels in the
FPGA fabric.
Example 6: Four Identical Channels in a Transceiver Block
Chapter 2: Transceiver Clocking in Arria II Devices
Figure
FPGA Fabric-Transceiver Interface Clocking
2–24. Use the tx_clkout[0]
December 2010 Altera Corporation
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