EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 545
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–15. Quartus II Assignments for Example 10 for Arria II Devices
December 2010 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the rx_clkout[9] signal.
Assignment
Table
2–15:
Figure 2–30. Sixteen Channels Across Four Transceiver Blocks for Example 10
Table 2–15
scheme shown in
top_level/top_xcvr_instance1/altgx_component/rx_clkout[9]
rx_datain[15..0]
GXB 0 PPM Core Clock Setting
ON
Figure 2–30
four transceiver blocks. The incoming serial data to all 16 channels have a 0 PPM
frequency difference with respect to each other. The rx_coreclk ports of all 16
channels are connected together and driven by rx_clkout[9] in transceiver block
GXBL2. The rx_clkout[9] also clocks the receiver data and status signals of all 16
channels in the FPGA fabric. Only one global or regional clock resource is used by
rx_clkout[9] with this clocking scheme.
Example 10: Sixteen Channels Across Four Transceiver Blocks
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
lists the Quartus II assignments that you must make for the clocking
shows 16 non-bonded channels without rate matcher located across
Figure
2–30.
rx_clkout[15:12]
rx_clkout[11:8]
rx_clkout[7:4]
rx_clkout[3:0]
Description
rx_coreclk[15:12]
rx_coreclk[11:8]
rx_coreclk[7:4]
rx_coreclk[3:0]
rx_clkout[9]
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Status
(1)
and Status
and Status
and Status
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
2–55
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