EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 463
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
- Current page: 463 of 692
- Download datasheet (22Mb)
Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–73. SONET/SDH OC-48 Datapath
Figure 1–74. SONET/SDH OC-96 Datapath
December 2010 Altera Corporation
tx_coreclk
tx_coreclk
rx_coreclk
rx_coreclk
FPGA
Fabric
FPGA
Fabric
FPGA Fabric-Transmitter
FPGA Fabric-Transmitter
SONET/SDH OC-48 Datapath
Figure 1–73
mode.
SONET/SDH OC-96 Datapath
Figure 1–74
mode.
FPGA Fabric-Receiver
FPGA Fabric-Receiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
shows the transceiver datapath when configured in SONET/SDH OC-48
shows the transceiver datapath when configured in SONET/SDH OC-96
tx_clkout
rx_clkout
tx_clkout
rx_clkout
Compensation
Compensation
RX Phase
RX Phase
FIFO
FIFO
Compensation
Compensation
wrclk
wrclk
TX Phase
TX Phase
FIFO
FIFO
rdclk
rdclk
Ordering
Byte
wrclk
wrclk
Serializer
Serializer
Transmitter Channel PCS
Transmitter Channel PCS
Byte De-
serializer
Byte De-
serializer
Byte
Byte
/2
/2
/2
/2
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
rdclk
Recovered Clock
Recovered Clock
Parallel
Parallel
Aligner
Aligner
Word
Word
Arria II Device Handbook Volume 2: Transceivers
Receiver Channel PMA
Receiver Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Serializer
Serializer
De-
De-
Serializer
Serializer
Divider
Divider
Clock
Clock
Local
Local
CDR
CDR
High-Speed
Serial Clock
High-Speed
Serial Clock
1–77
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