EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 450
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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1–64
Table 1–15. Supported Features in PCIe Mode for Arria II Devices (Part 2 of 2)
Figure 1–62. Arria II GX and GZ Transceiver Datapath in PCIe Mode
Notes to
(1) The transceiver datapath clock varies between non-bonded (×1) and bonded (×4 and ×8) configurations in PCIe mode, described in the
(2) The word aligner uses automatic synchronization state machine mode (10-Bit /K28.5/).
(3) This can be ×1, ×4, or ×8 at 2.5 Gbps or ×1 or ×4 at 5.0 Gbps (for Arria II GZ devices only).
(4) The high-speed serial clock is running at 1.25 GHz.
(5) The parallel clocks are running at 250 MHz.
(6) This clock is running at 125 MHz if the byte serializer and deserializer are used. Otherwise, this clock is running at 250 MHz.
(7) If you use the PCIe hard IP, you can enable the byte serializer and deserializer with an 8-bit FPGA fabric-to-transceiver interface running at 250 MHz
Arria II Device Handbook Volume 2: Transceivers
Dynamic switch between 2.5 Gbps and 5 Gbps signaling rate
Dynamically selectable transmitter margining for differential output voltage
control
Dynamically selectable transmitter buffer de-emphasis of -3.5 db and -6 db
Note to
(1) For Arria II GZ devices only.
(6)
Fabric
FPGA
Clocking for Arria II Devices
or disabled with a 16-bit FPGA fabric-to-transceiver interface running at 125 MHz. Otherwise, these blocks are always disabled and your 16-bit
FPGA fabric-to-transceiver interface is running at 125 MHz.
Figure
Figure
8-Bit Interface @ 250 MHz or 16-Bit Interface @ 125 MHz
1–15:
1–62:
Figure 1–62
PCIe functional mode.
chapter.
(6)
(6)
(6)
Feature
tx_clkout[0]
Compensation
wrclk
shows the Arria II GX and GZ transceiver datapath when configured in
TX Phase
FIFO
(6)
rdclk
/2
wrclk
Byte Serializer
(7)
/2
Receiver Channel PCS
Transmitter Channel PCS
rdclk
(Note 1)
Chapter 1: Transceiver Architecture in Arria II Devices
8B/10B Encoder
2.5 Gbps (Gen1)
Low-Speed Parallel Clock (5)
Low-Speed Parallel Clock (5)
Parallel Recovery Clock (5)
—
—
—
December 2010 Altera Corporation
5.0 Gbps (Gen2)
Interface
10-Bit
Transmitter Channel
Receiver Channel
Functional Modes
v
v
v
Serial Clock (4)
High-Speed
PMA
PMA
Transceiver
(1)
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