EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 429

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
December 2010 Altera Corporation
Figure 1–42
code group into an 8-bit data code group (8'hBC) driven on the rx_dataout port. The
rx_ctrldetect signal is asserted high synchronous with 8'hBC on the rx_dataout
port, indicating that it is a control code group. The rest of the codes received are data
code groups /Dx.y/.
Figure 1–42. 8B/10B Decoder in Control Code Group Detection
Byte Deserializer
Some serial data rates violate the maximum frequency for the FPGA
fabric-to-transceiver interface. In such configurations, the byte deserializer is required
to reduce the FPGA fabric-to-transceiver interface frequency to half while doubling
the parallel data width. This module is optional in configurations that do not exceed
the FPGA fabric-to-transceiver interface clock upper frequency limit.
For example, at a 3.2 Gbps data rate with a deserialization factor of 10, the receiver
PCS datapath runs at 320 MHz. The byte serializer converts the 10-bit parallel
received data at 320 MHz into 20-bit parallel data at 160 MHz before forwarding it to
the FPGA fabric.
In Arria II GX devices, you cannot enable the byte deserializer in double-width mode.
However, in Arria II GZ devices, you can enable both double-width mode and the
byte deserializer to achieve a 32- or 40-bit PCS-FPGA interface.
Figure 1–43
PMA-to-PCS interface.
Figure 1–43. Byte Deserializer
rx_dataout[7:0]
rx_ctrldetect
shows the 8B/10B decoder decoding the received 10-bit /K28.5/ control
shows the block diagram of the byte deserializer with 8-bit or 10-bit
datain[9:0]
8-bit datain from the 8B/10B
Decoder or 10-bit datain
from the Word Aligner
clock
Receiver PCS Clock
rx_enabyteord
D3.4
83
D24.3
78
D28.5
BC
Serializer
Byte
/2
K28.5
BC
D15.0
Arria II Device Handbook Volume 2: Transceivers
rx_byteorderalignstatus
0F
16-bit or 20-bit output to the
Byte Ordering or RX Phase
Compensation FIFO
D0.0
00
D31.5
BF
D28.1
3C
1–43