EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 583
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 4: Reset Control and Power Down in Arria II Devices
Transceiver Reset Sequences
Figure 4–5. Sample Reset Sequence of Four Receiver and Transmitter Channels—Receiver CDR in Manual Lock Mode
Note to
(1) For the transceiver block power down duration, refer to the
December 2010 Altera Corporation
Reset Signals
CDR Control Signals
Output Status Signals
Figure
rx_locktorefclk[0]
rx_locktorefclk[3]
4–5:
rx_locktodata[0]
rx_locktodata[3]
pll_powerdown
rx_analogreset
rx_pll_locked[0]
rx_pll_locked[3]
rx_digitalreset
tx_digitalreset
pll_locked
busy
5. Wait for the rx_freqlocked signal from each channel to go high. The
6. In a bonded channel group, when the rx_freqlocked signals of all the channels
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. For XAUI
functional mode, with the receiver CDR in manual lock mode, use the reset sequence
shown in
1
rx_freqlocked signal of each channel may go high at different times (indicated by
the slashed pattern at marker 7).
have gone high, from that point onwards, wait for at least 4 s for the receiver
parallel clock to be stable, then de-assert the rx_digitalreset signal (marker 8).
At this point, all the receivers are ready for data traffic.
1 μs (1)
Figure
2
4–5.
3
Two parallel clock cycles
4
Device Datasheet for Arria II Devices
5
6
7
7
15 μs (1)
8
8
8
8
4 μs (1)
Arria II Device Handbook Volume 2: Transceivers
chapter in the Arria II Device Handbook.
9
4–9
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