EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 21

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
Figure 1–2. Architecture Overview for Arria II GZ Device
Notes to
(1) Not available for 780-pin FBGA package.
(2) Not available for 780-pin and 1152-pin FBGA packages.
December 2010 Altera Corporation
Figure
High-Speed Transceiver Features
1–2:
Arria II GX devices integrate up to 16 transceivers and Arria II GZ devices up to 24
transceivers on a single device. The transceiver block is optimized for cost and power
consumption. Arria II transceivers support the following features:
■
■
■
Configurable pre-emphasis and equalization, and adjustable output differential
voltage
Flexible and easy-to-configure transceiver datapath to implement proprietary
protocols
Signal integrity features
■
■
■
■
General Purpose I/O and
with DPA and Soft CDR
High-Speed LVDS I/O
Programmable transmitter pre-emphasis to compensate for inter-symbol
interference (ISI)
User-controlled receiver equalization with up to 7 dB (Arria II GX) and
16 dB (Arria II GZ) of high-frequency gain
On-die power supply regulators for transmitter and receiver PLL charge pump
and voltage-controlled oscillator (VCO) for superior noise immunity
Calibration circuitry for transmitter and receiver on-chip termination (OCT)
resistors
Transceiver Block
PLL (1)
PLL (2)
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
(Logic Elements, DSP,
Arria II GZ FPGA Fabric
Embedded Memory,
Clock Networks)
400 Mbps-6.375 Gbps CDR-based Transceiver
General Purpose I/O and 150 Mbps-1.25 Gbps
LVDS interface with DPA and Soft-CDR
PLL PLL
PLL PLL
Arria II Device Handbook Volume 1: Device Interfaces and Integration
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
PLL (1)
PLL (2)
1–7