EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 675
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices
Table 1–55. DPA Lock Time Specifications for Arria II Devices
December 2010 Altera Corporation
Sampling Window
(SW)
Notes to
(1) When J = 3 to 10, use the SERDES block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
(5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This only applies to DPA and soft-CDR modes.
(10) This only applies to LVDS source synchronous mode.
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in the table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
Standard
Symbol
Table
Table
1–54:
1–55:
00000000001111111111
Table 1–55
Non-DPA mode
Training Pattern
Conditions
00001111
10010000
10101010
01010101
lists DPA lock time specifications for Arria II GX and GZ devices.
Min
—
Transitions in One
Repetition of the
Training Pattern
Number of Data
C3, I3
Typ
—
2
2
4
8
8
(Note
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
(Note 1), (2), (10)
Max
1), (2),
300
(3)
Repetitions per
Transitions
Min
Number of
—
256 Data
128
128
64
32
32
(Part 3 of 3)
C4, I4
Typ
(4)
—
640 data transitions
640 data transitions
640 data transitions
640 data transitions
640 data transitions
Max
300
Maximum
Unit
ps
1–71
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