EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 80
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4–8
DSP Block Resource Descriptions
Figure 4–5. Half-DSP Block Architecture
Notes to
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) When the chainout adder is not in use, the second adder register banks are known as output register banks.
(4) You must connect the chainin port to the chainout port of the previous DSP blocks; it must not be connected to general routings.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
chainin[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
4–5:
datab_1[ ]
dataa_2[ ]
scanina[ ]
(4)
The DSP block consists of the following elements:
■
■
■
■
■
■
Figure 4–5
DSP block.
loopback
Input register bank
Four two-multiplier adders
Pipeline register bank
Second-stage adders
Four rounding and saturation logic units
Second adder register and output register bank
scanouta
clock[3..0]
ena[3..0]
alcr[3..0]
Half-DSP Block
shows a detailed illustration of the overall architecture of the top half of the
Table 4–9 on page 4–30
chainout_saturate
chainout_round
zero_loopback
zero_chainout
accum_sload
lists the DSP block dynamic signals.
output_saturate
output_round
(3)
shift_right
rotate
signa
signb
chainout
Chapter 4: DSP Blocks in Arria II Devices
overflow (1)
chainout_sat_overflow (2)
December 2010 Altera Corporation
result[ ]
DSP Block Resource Descriptions
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