EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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1–2
Arria II Device Handbook Volume 1: Device Interfaces and Integration
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Maximum system bandwidth
■
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Complete PIPE protocol solution with an embedded hard IP block that provides
physical interface and media access control (PHY/MAC) layer, Data Link layer,
and Transaction layer functionality
Optimized for high-bandwidth system interfaces
■
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Low power
■
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Advanced usability and security features
■
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Emulated LVDS output support with a data rate of up to 1152 Mbps
Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting
rates between 155 Mbps and 6.375 Gbps
Dedicated circuitry to support physical layer functionality for popular serial
protocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, Serial
RapidIO
SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI
(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,
SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter
(JESD204), and SFI-5.
Up to 726 user I/O pins arranged in up to 20 modular I/O banks that support a
wide range of single-ended and differential I/O standards
High-speed LVDS I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry at data rates from 150 Mbps to
1.25 Gbps
Architectural power reduction techniques
Typical physical medium attachment (PMA) power consumption of 100 mW at
3.125 Gbps.
Power optimizations integrated into the Quartus II development software
Parallel and serial configuration options
On-chip series (R
for single-ended I/Os and on-chip differential (R
I/O
256-bit advanced encryption standard (AES) programming file encryption for
design security with volatile and non-volatile key storage options
Robust portfolio of IP for processing, serial protocols, and memory interfaces
Low cost, easy-to-use development kits featuring high-speed mezzanine
connectors (HSMC)
®
(SRIO), Common Public Radio Interface (CPRI), OBSAI,
S
) and on-chip parallel (R
Chapter 1: Overview for the Arria II Device Family
T
) termination with auto-calibration
D
) termination for differential
December 2010 Altera Corporation
Arria II Device Feature
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