EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 247
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
LVDS SERDES and DPA Block Diagram
LVDS SERDES and DPA Block Diagram
Figure 8–3. LVDS SERDES and DPA Block Diagram
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, two PLLs
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
December 2010 Altera Corporation
on the right side of the device are required.
Figure
rx_divfwdclk
rx_outclock
tx_coreclock
8–3:
Fabric
FPGA
rx_out
tx_in 10
10
The Arria II GX devices have dedicated SERDES and DPA circuitry for LVDS
transmitters and receivers on the right side. The Arria II GZ devices have dedicated
SERDES and DPA circuitry for LVDS transmitters and receivers on the row I/O banks.
Figure 8–3
interface signals for the transmitter and receiver datapaths. For more information,
refer to
page
8–11.
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
“Differential Transmitter” on page 8–8
2
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
shows the LVDS SERDES and DPA block diagram. This diagram shows the
tx_coreclock)
DIN
IOE
2
2
PLL (4)
Clock Multiplexer
3
DOUT
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
(Note
diffioclk
DIN
1), (2),
rx_inclock/tx_inclock
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DOUT
(3)
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
and
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
“Differential Receiver” on
DPA Clock
DPA Circuitry
Data
LVDS Transmitter
DIN
LVDS Receiver
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
rx_in
tx_out
8–7
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