EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 401
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Arria II Devices
Transmitter Channel Datapath
December 2010 Altera Corporation
w
8B/10B Encoder
Figure 1–14
Figure 1–14. 8B/10B Encoder
The 8B/10B encoder generates 10-bit code groups from the 8-bit data and 1-bit control
identifier. If the tx_ctrlenable input is high, the 8B/10B encoder translates the 8-bit
input data to a 10-bit control word (Kx.y). Otherwise, the 8B/10B encoder translates
the 8-bit input data to a 10-bit data word (Dx.y).
how the second 8'hBC data is encoded as a control word, while the reset of the data
are encoded as a data word.
Figure 1–15. Control Word and Data Word Transmission
The IEEE 802.3 8B/10B encoder specification identifies only a set of 8-bit characters
for which tx_ctrlenable should be asserted. If you assert tx_ctrlenable for any
other set of characters, the 8B/10B encoder might encode the output 10-bit code as an
invalid code (it does not map to a valid Dx.y or Kx.y code), or an unintended valid
Dx.y code, depending on the value entered. It is possible for a downstream 8B/10B
decoder to decode an invalid control word into a valid Dx.y code without asserting
any code error flags. Altera recommends not asserting tx_ctrlenable for
unsupported 8-bit characters.
tx_datain[7:0]
tx_ctrlenable
shows the inputs and outputs of the 8B/10B encoder.
code group
clock
tx_invpolarity
tx_ctrlenable
tx_forcedisp
tx_dispval
FIFO or Byte Serializer
Phase Compensation
Input Data from TX
D3.4
83
D24.3
78
8B/10B Encoder
D28.5
BC
K28.5
BC
Figure 1–15
D15.0
0F
Arria II Device Handbook Volume 2: Transceivers
Output Data to
Serializer (tx_dataout)
D0.0
00
shows an example of
D31.5
BF
D28.1
3C
1–15
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