EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 83
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Arria II Devices
DSP Block Resource Descriptions
December 2010 Altera Corporation
Multiplier and First-Stage Adder
1
The multiplier stage supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers. Other
word lengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 is padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number.
Table 4–4
representations. If any one of the operands is a signed value, the result of the
multiplication is signed.
Table 4–4. Multiplier Sign Representation for Arria II Devices
Each half block has its own signa and signb signal. Therefore, all data A inputs
feeding the same half-DSP block must have the same sign representation. Similarly, all
data B inputs feeding the same half-DSP block must have the same sign
representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 × 18 loopback and
two-multiplier adder modes. For more information, refer to
Sum Mode” on page
By default, when the signa and signb signals are unused, the Quartus II software sets
the multiplier to perform unsigned multiplication.
Figure 4–5 on page 4–8
that can feed into the first-stage adder. There are four first-stage adders in a DSP block
(two adders per half-DSP block). The first-stage adder block has the ability to perform
addition and subtraction. The control signal for addition or subtraction is static and
you must configure after compilation. The first-stage adders are used by the sum
modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, rounding and saturation unit, or
the output registers.
Data A (signa Value)
Unsigned (logic 0)
Unsigned (logic 0)
lists the sign of the multiplication result for the various operand sign
Signed (logic 1)
Signed (logic 1)
4–20.
shows that the outputs of the multipliers are the only outputs
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Data B (signb Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
4–14. Depending on the data width of the
“Two-Multiplier Adder
Unsigned
Result
Signed
Signed
Signed
4–11
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